The present invention relates to the field of power converters, and in particular to a hysteretic converter wherein correction for the offset from a target voltage is supplied.
Various schemes of controlling a DC to DC power converter are known. Typically, one of output voltage and output current are sensed and fedback to the controller via an error amplifier, the error amplifier arranged to operate in a linear mode. A reference value, reflective of a target output, is further received by the error amplifier, and differences in output from the target output are detected and compensated for, typically by adjusting the amount of time that an electronically controlled switch is closed. In such an embodiment, the output voltage or current varies about the target output, and the average output over time may equal the target output. Such a linear regulation control however is inappropriate when a quick reaction to large changes in load is required.
In order to overcome this difficulty, a hysteretic converter is utilized. The hysteretic converter comprises at least one electronically controlled switch, a comparator and an inductor, the electronically controlled switch being closed responsive to the output of the comparator. The comparator is arranged to close the electronically controlled switch promptly responsive to the instantaneous output voltage falling below a first reference signal, thus driving the output voltage higher without the delay of an integrator or other low bandwidth circuitry. Various schemes for opening the electronically controlled switch exist, including, but not limited to, comparing the output voltage to a second reference and defining a predetermined fixed on time for the electronically controlled switch.
FIG. 1A illustrates a high level schematic diagram of a hysteretic converter 10 of the prior art, and FIG. 1B illustrates certain waveforms of hysteretic converter 10 of FIG. 1A, with the x-axis representing time and the y-axis representing the amplitude of output voltage VOUT, FIGS. 1A and 1B being described herein together. Hysteretic converter 10 comprises: a comparator 20 illustrated as a Schmidt trigger comparator; an RS flip flop 30; an off time control circuit 40; a switched mode power supply 50, illustrated without limitation without limitation as a buck converter constituted of an electronically controlled switch 60, an inductor 70, a unidirectional electronic valve 80 illustrated without limitation as a diode and an output capacitor 90. Additionally a load 100 is further illustrated. An input voltage VIN is connected to a first end of electronically controlled switch 60, and a second end of electronically controlled switch 60 is connected to a first end of inductor 70 and to the cathode of unidirectional electronic valve 80. A second end of inductor 70, denoted output voltage VOUT, is connected to a first end of output capacitor 90 and to a first end of load 100. A second end of load 100, a second end of output capacitor 90 and the anode of unidirectional electronic valve 80 are commonly connected.
Output voltage VOUT is connected to the inverting input of comparator 20 via a feedback circuit 25, and a reference voltage REF is connected to the non-inverting input of comparator 20. The output of comparator 20 is connected to the set input of RS flip flop 30 and the Q output of RS flip flop 30 is connected to the control input of electronically controlled switch 60 of switched mode power supply 50. An input of off time control circuit 40 is connected to the Q output of RS flip flop 30, and the output of off time control circuit 40 is connected to the reset input of RS flip flop 30. Output voltage VOUT is illustrated as being fed directly to the inverting input of comparator 20, however this is not meant to be limiting in any way, and in an exemplary embodiment a function of output voltage VOUT, such as a voltage divided output consonant with reference voltage REF is fed back to the input of comparator 20, preferably any function being without active devices which result in a reduced bandwidth for response to changes in load 100.
In operation, when output voltage VOUT falls to less than the threshold value signal fed to the non-inverting input of comparator 20, i.e. reference voltage REF, comparator 20 closes electronically controlled switch 60 by setting RS flip flop 30 thus increasing output voltage VOUT. Electronically controlled switch 60 remains closed after output voltage VOUT is increased by the latching action of RS flip flop 30. Off time control circuit 40, illustrated without limitation as a fixed on time timer, shuts off electronically controlled switch 60 after a predetermined interval, thus allowing output voltage VOUT to again fall responsive to the draw of load 100. Off time control circuit 40 may be replaced with a fixed off time circuitry, or a high side comparator, without limitation. The arrangement of the feedback circuit, comparator 20 and electronically controlled switch 60 is known as a hysteretic loop and responds rapidly to changes in VOUT. Output voltage VOUT swings between the threshold value signal reference voltage REF and an upper limit set by off time control circuit 40, with the voltage swing denoted VRIPPLE. The average output voltage, denoted AVG_VOUT, is equal to: REF+ 1/2  (VRIPPLE), i.e. it is offset from reference voltage REF by 1/2  of the ripple voltage.
Thus, the value of average output voltage AVG_VOUT is not directly controlled by reference voltage REF, but is instead a function of the ripple voltage. What is desired, and not provided by the prior art, is a mechanism to directly control average output voltage AVG_VOUT in a hysteretic controller, while still maintaining the immediate response to load transients of the hysteretic controller.